/*====================================================================== A driver for the PCI NinjaSCSI32bi SCSI Host Adapter nins32.h 0.2 2000/06/16 The contents of this file are subject to the Mozilla Public License Version 1.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.mozilla.org/MPL/ Software distributed under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for the specific language governing rights and limitations under the License. ======================================================================*/ // -------------------------------------------------------- // -------------------------------------------------------- // typedef ------------------------------------------------ // -------------------------------------------------------- // -------------------------------------------------------- #define MMAPIO typedef unsigned short WORD; typedef unsigned long DWORD; typedef unsigned char UCHAR; typedef unsigned char BYTE; typedef unsigned short USHORT; typedef USHORT *PUSHORT; typedef DWORD ULONG; typedef ULONG *PULONG; typedef UCHAR *PUCHAR; typedef char CHAR; typedef CHAR *PCHAR; typedef long LONG; typedef int boolean; typedef unsigned char BOOL; typedef unsigned char BOOLEAN; typedef BOOLEAN *PBOOLEAN; typedef void VOID; typedef VOID *PVOID; typedef void* PTR; #define IN #define OUT #define STATIC static // -------------------------------------------------------- // -------------------------------------------------------- // define ------------------------------------------------ // -------------------------------------------------------- // -------------------------------------------------------- #define max(a,b) (((a) > (b)) ? (a) : (b)) #define min(a,b) (((a) < (b)) ? (a) : (b)) #define BASE_PORT 0x180 #define NUMBR_PORTS 0x10 #define BASE_WIDTH 0x10 #define SCSI_PORT 0x0 // // Input status bit definitions. // #define S_ATN 0x80 // #define S_SELECT 0x40 // #define S_REQUEST 0x20 // Request line from SCSI bus #define S_ACK 0x10 // Acknowlege line from SCSI bus #define S_BUSY 0x08 // Busy line from SCSI bus #define S_CD 0x04 // Command/Data line from SCSI bus #define S_IO 0x02 // Input/Output line from SCSI bus #define S_MESSAGE 0x01 // Message line from SCSI bus // // Useful Bus Monitor status combinations. // #define BM_BUS_FREE 0 #define BM_COMMAND ( S_BUSY | S_CD | S_REQUEST ) #define BM_MESSAGE_IN ( S_BUSY | S_MESSAGE | S_IO | S_CD | S_REQUEST ) #define BM_MESSAGE_OUT ( S_BUSY | S_MESSAGE | S_CD | S_REQUEST ) #define BM_DATA_IN ( S_BUSY | S_IO | S_REQUEST ) #define BM_DATA_OUT ( S_BUSY | S_REQUEST ) #define BM_STATUS ( S_BUSY | S_IO | S_CD | S_REQUEST ) #define BM_RESELECT ( S_SELECT | S_IO ) #define BP_COMMAND ( S_CD ) #define BP_MESSAGE_IN ( S_MESSAGE | S_IO | S_CD ) #define BP_MESSAGE_OUT ( S_MESSAGE | S_CD ) #define BP_DATA_IN ( S_IO ) #define BP_DATA_OUT ( 0 ) #define BP_STATUS ( S_IO | S_CD ) // // Status mask for bus phase. // #define S_PHASE_MASK ((UCHAR) 0x3f) #define SCSI_READ_PHASE(BASE) ((UCHAR) (SCSI_READ_STATUS(BASE) & S_PHASE_MASK)) // // SCSI source identifier for host system. // #define SCSI_INITIATOR_ID 7 #define SCSI_IDT_VECTOR 5 // // Various timeout values (in microseconds). // //#define REQUEST_SPIN_WAIT 40000000 // Wait for target to assert REQUEST #define REQUEST_SPIN_WAIT 40000 // Wait for target to assert REQUEST #define RESET_HOLD_TIME 25 // Time to hold RESET line to reset bus #define RESET_RECOVER_TIME 2500000 #define BUS_FREE_DELAY 100000 // Wait for BUS_FREE condition // // Number of adapters this driver will support. // #define MAX_ADAPTERS 1 // // Limit transfer length to 64 Kbytes // #define MAX_TRANSFER_LENGTH ( 64 * 1024 ) #ifdef NINS32DBG LONG INT_POLL_SEL = 10; LONG INT_POLL_IRQ = 10; #else #define INT_POLL_SEL 10 #define INT_POLL_IRQ 10 #endif /**/ /* SCSI bus status codes.*/ /**/ /* Status Byte in scsiall.h*/ #define SCSI_CONDITION_MET 0x04 #define SCSI_INTERMEDIATE_COND_MET 0x14 #define SCSI_RESERVATION_CONFLICT 0x18 #define SCSI_COMMAND_TERMINATED 0x22 /* * Status Byte */ #define SCSI_OK 0x00 #define SCSI_CHECK 0x02 #define SCSI_BUSY 0x08 #define SCSI_INTERM 0x10 #define SCSI_QUEUE_FULL 0x28 /* SCSI Extended Message Lengths*/ /**/ #define SCSIMESS_MODIFY_DATA_LENGTH 5 #define SCSIMESS_SYNCH_DATA_LENGTH 3 #define SCSIMESS_WIDE_DATA_LENGTH 2 // // SCSI bus status codes. // #define SCSISTAT_GOOD 0x00 #define SCSISTAT_CHECK_CONDITION 0x02 #define SCSISTAT_CONDITION_MET 0x04 #define SCSISTAT_BUSY 0x08 #define SCSISTAT_INTERMEDIATE 0x10 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 #define SCSISTAT_RESERVATION_CONFLICT 0x18 #define SCSISTAT_COMMAND_TERMINATED 0x22 #define SCSISTAT_QUEUE_FULL 0x28 #define MSG_IDENTIFYFLAG_WITH_DISCON 0XC0 /* scsi_message.h */ /* Messages (1 byte) */ /* I/T (M)andatory or (O)ptional */ #define MSG_CMDCOMPLETE 0x00 /* M/M */ #define MSG_EXTENDED 0x01 /* O/O */ #define MSG_SAVEDATAPOINTER 0x02 /* O/O */ #define MSG_RESTOREPOINTERS 0x03 /* O/O */ #define MSG_DISCONNECT 0x04 /* O/O */ #define MSG_INITIATOR_DET_ERR 0x05 /* M/M */ #define MSG_ABORT 0x06 /* O/M */ #define MSG_MESSAGE_REJECT 0x07 /* M/M */ #define MSG_NOOP 0x08 /* M/M */ #define MSG_PARITY_ERROR 0x09 /* M/M */ #define MSG_LINK_CMD_COMPLETE 0x0a /* O/O */ #define MSG_LINK_CMD_COMPLETEF 0x0b /* O/O */ #define MSG_BUS_DEV_RESET 0x0c /* O/M */ #define MSG_ABORT_TAG 0x0d /* O/O */ #define MSG_CLEAR_QUEUE 0x0e /* O/O */ #define MSG_INIT_RECOVERY 0x0f /* O/O */ #define MSG_REL_RECOVERY 0x10 /* O/O */ #define MSG_TERM_IO_PROC 0x11 /* O/O */ /* Messages (2 byte) */ #define MSG_SIMPLE_Q_TAG 0x20 /* O/O */ #define MSG_HEAD_OF_Q_TAG 0x21 /* O/O */ #define MSG_ORDERED_Q_TAG 0x22 /* O/O */ #define MSG_IGN_WIDE_RESIDUE 0x23 /* O/O */ /* Identify message */ #define MSG_IDENTIFYFLAG 0x80 #define MSG_IDENTIFY(lun, disc) (((disc) ? 0xc0 : MSG_IDENTIFYFLAG) | (lun)) #define MSG_ISIDENTIFY(m) ((m) & MSG_IDENTIFYFLAG) /* Extended messages (opcode and length) */ #define MSG_EXT_SDTR 0x01 #define MSG_EXT_SDTR_LEN 0x03 #define MSG_EXT_WDTR 0x03 #define MSG_EXT_WDTR_LEN 0x02 #define SCSIMESS_MODIFY_DATA_POINTER 0X00 #define SCSIMESS_SYNCHRONOUS_DATA_REQ 0X01 #define SCSIMESS_WIDE_DATA_REQUEST 0X03 #define READ_XFER_CNT 512 #define WRITE_BURST_CNT 512 //64 #define WRITE_SPOT_CNT 32 //64 #define ASYNCHRONOUS_OFFSET 0 #define ASYNCHRONOUS_PERIOD 0 #define SYNCHRONOUS_OFFSET 15 #define SYNCHRONOUS_PERIOD 0x0c #define SYNCHRONOUS_PERIOD_5M 0x32 #define SYNCHRONOUS_PERIOD_10M 0x19 #define SYNCHRONOUS_PERIOD_20M 0x0c #define XMODE_MMIO 5 #define XMODE_PIOBM 4 #define XMODE_DMA 3 #define XMODE_FIFO 2 #define XMODE_PIO 1 #define XMODE_PIO32 0 #define MAX_SG_LIST 18 #define BM_LAST 0x80000000 #define FIFO_SIZE 128 #define INT_POLL_SEL 10 #define INT_POLL_IRQ 10 // //define adapter type // #define OPT_NON_DISCONECT 0x0001 #define OPT_TUNEUP_DI 0x0002 #define OPT_PCIC_SPEED 0x0004 #define OPT_MMIO_SPEED 0x0008 #define OPT_NO_ATN 0x0010 #define OPT_ULTRA 0x0020 #define OPT_AUTOPARA 0x0040 #define OPT_NOSG 0x0080 #define OPT_DO_NOT_WRT_DISCONECT 0x0100 //*[v0.93] for ToPic95 // // specific port driver device extension flags. // #define PD_PENDING_START_IO 0x0004 #define PD_ADAPTER_RESET_MASK ( PD_PENDING_START_IO ) // // Define target controller specific flags. // #define PD_SYNCHRONOUS_NEGOTIATION_DONE 0x0001 #define PD_DO_NOT_NEGOTIATE 0x0002 #define PD_SYNCHRONOUS_TRANSFER_SENT 0X0004 #define PD_NONCACHE 0X0008 #ifdef NINJA32UDE #define PD_WIDEDATA_TRANSFER_SENT 0X0010 //+[ude] #define PD_DUALEDGE_ENABLE 0x0020 //+[ude] #define PD_DUALEDGE_TEST 0x0040 //+[ude] #endif // NINJA32UDE #define PCI_VENDOR_ID_IODATA 0x10FC #define PCI_VENDOR_ID_WORKBIT 0x1145 #define PCI_DEVICE_ID_IODATA_NJS32BI 0x0005 #define PCI_DEVICE_ID_WORKBIT_NJS32BI 0x8007 #define PCI_DEVICE_ID_KME_NJS32BI 0xF007 #define PCI_DEVICE_ID_LOGITEC_TEST 0xF010 #define PCI_DEVICE_ID_LOGITEC_NJS32BI 0xF012 #define PCI_DEVICE_ID_LOGITEC_NJS32BIB 0xF013 #define PCI_VENDOR_ID_ALADIN_MB 0x10B9 #define PCI_DEVICE_ID_ALADIN_MB 0x0005 #define PCI_VENDOR_ID_ToPIC95 0x1179 #define PCI_DEVICE_ID_ToPIC95 0x060A /* 0608 */ // -------------------------------------------------------- // -------------------------------------------------------- // struct ------------------------------------------------ // -------------------------------------------------------- // -------------------------------------------------------- #ifdef USE_PRAGMAPACK #pragma pack() #pragma pack(1) #endif // USE_PRAGMAPACK // // **** SCSI PORT ***** // typedef struct _SCSI_REGISTER { union { USHORT pIrqControl; // #0 USHORT pIrqStatus; } irq; union { USHORT pTransferControl; // #2 USHORT pTransferStatus; }trans; USHORT pIndexReg; // #4 union { USHORT pTimerSet; // #6 USHORT pTimerRead; }timer; USHORT pDataRegL; // #8 USHORT pDataRegH; // #a USHORT pFifoRestCnt; // #c UCHAR pReserved0e; // #e UCHAR pSreqSmplRate; // #f UCHAR pScsiBusCtrl; // #10 UCHAR pReserved2; // #11 union { UCHAR pClearCounter; // #12 UCHAR pScsiBusMonitor; }sc; UCHAR pReserved13; // #13 UCHAR pCommandData; // #14 UCHAR pReserved15; // #15 union { UCHAR pParityControl; // #16 UCHAR pParityStatus; }parity; UCHAR pReserved17; // #17 union commandControl{ USHORT pCommandControl; // #18 struct reselectId{ UCHAR pReselectId; UCHAR pReserved19; } reselect; }_18; union zzzs { UCHAR pSetArbit; // #1a UCHAR pArbitStatus; }_1a; UCHAR pReserved1b; UCHAR pSyncReg; // #1c UCHAR pAckWidth; // #1d UCHAR pReserved1e; UCHAR pReserved1f; UCHAR pScsiDataWithAck; // #20 UCHAR pReserved21; union { UCHAR pScsiOutLatch; UCHAR pTargetId; // #22 UCHAR pScsiDataIn; } _22; UCHAR pReserved23; union { UCHAR pScamControl; // #24 UCHAR pScamStatus; } scam; UCHAR pReserved25; UCHAR pScamData; // #26 UCHAR pReserved27; ULONG pSackCnt; // #28 ULONG pSreqCnt; // #2c union { struct { UCHAR pbFifoData; // #30 UCHAR pbFifoData1; UCHAR pbFifoData2; // #32 UCHAR pbFifoData3; }b; struct { USHORT pwFifoData0; USHORT pwFifoData1; }w; ULONG pwFifoData; // #30 } _30; ULONG pBmStartAdr; // #34 ULONG pBmCnt; // #38 ULONG pSgAdr; // #3c USHORT pScsiExecutePhase; // #40 UCHAR pScsiCsbIn; // #42 UCHAR pReserved43; ULONG pScsiMsgOut; // #44 USHORT pSelTimeOut; // #48 UCHAR pReserved4a; UCHAR pReserved4b; ULONG pSavedSackCnt; // #4c #ifdef NINJA32UDE ULONG HtoSDataDelay; // #50 new vvvv ULONG StoHDataDelay; // #54 ULONG AckSumCheckRd; // #58 ULONG ReqSumCheckRd; // #5c new ^^^^ #endif // NINJA32UDE } SCSI_REGISTER, *PSCSI_REGISTER; typedef struct _SUBREGS { UCHAR pClockDiv; // #00 UCHAR pTermPwrCtrl; // #01 UCHAR pExtPortDdr; // #02 UCHAR pExtPort; // #03 UCHAR pIrqSelect; // #04 UCHAR pOldScsiPhase; // #05 UCHAR pFifoFullShld; // #06 UCHAR pFifoEmptyShld; // #07 UCHAR pExpRomControl; // #08 UCHAR pExpRomAdr; // #09 UCHAR pExpRomData; // #0a UCHAR pChipMode; // #0b UCHAR pMiscReg; // #0c UCHAR pBmCycle; // #0d UCHAR pReserved0e; // #0e UCHAR pUpCnt; // #0f UCHAR pCfgCmdStr; // #10 UCHAR pCfgLataCache; // #11 UCHAR pCfgBaseAdr1; // #12 UCHAR pCfgBaseAdr2; // #13 UCHAR pCfgIntLine; // #14 #ifdef NINJA32UDE UCHAR pSerialRomCtl; // #15 new UCHAR pFifoHstPointer; // #16 UCHAR pSReqDelay; // #17 new vvv UCHAR pSAckDelay; // #18 UCHAR pSReqNoiseCancel; // #19 UCHAR pSdpNoiseCancel; // #1a UCHAR pDelayTest; // #1b UCHAR pReserved1c; UCHAR pReserved1d; UCHAR pReserved1e; UCHAR pReserved1f; UCHAR pSd0NoiseCancel; // #20 UCHAR pSd1NoiseCancel; // #21 UCHAR pSd2NoiseCancel; // #22 UCHAR pSd3NoiseCancel; // #23 UCHAR pSd4NoiseCancel; // #24 UCHAR pSd5NoiseCancel; // #25 UCHAR pSd6NoiseCancel; // #26 UCHAR pSd7NoiseCancel; // #27 new ^^^ #else // NINJA32UDE UCHAR pReserved15; // #15 UCHAR pFifoHstPointer; // #16 #endif // NINJA32UDE } SUBREGS, *PSUBREGS; typedef struct _IRQ_STATUS { // #0 USHORT LatchedMSG : 1; USHORT LatchedI_O : 1; USHORT LatchedC_D : 1; USHORT LatchBusFree : 1; USHORT ReselectIrq : 1; USHORT PhaseChgIrq : 1; USHORT ScsiResetIrq : 1; USHORT TimerIrq : 1; USHORT FifoShldIrq : 1; USHORT CardBusIrq : 1; USHORT BmCntErrIrq : 1; USHORT AutoScsiIrq : 1; USHORT CardBusIrqMask : 1; USHORT TimerIrqMask : 1; USHORT FifoIrqMask : 1; USHORT ScsiIrqMask : 1; } IRQ_STATUS, *PIRQ_STATUS; typedef struct _IRQ_CONTROLP { // #0 USHORT Reserved1 : 12; USHORT CardBusIrqMask : 1; USHORT TimerIrqMask : 1; USHORT FifoIrqMask : 1; USHORT ScsiIrqMask : 1; } IRQ_CONTROLP, *PIRQ_CONTROLP; typedef struct _TRANSFER_CONTROL { // #2 #ifdef NINJA32UDE USHORT CB_MMIO_Mode : 1; USHORT CB_PIO_Mode : 1; USHORT BMTest : 1; USHORT BMTestDir : 1; USHORT DualAgeEnable : 1; // new USHORT NoXferHost : 1; // new USHORT reserved : 1; USHORT TransferGo : 1; #else // NINJA32UDE USHORT CB_MMIO_Mode : 1; USHORT CB_PIO_Mode : 1; USHORT Reserved2 : 5; USHORT TransferGo : 1; #endif // NINJA32UDE USHORT BlindMode : 1; USHORT BmStart : 1; USHORT AdvancedBmWrite : 1; USHORT BmSingleMode : 1; USHORT Reserved3 : 2; USHORT AllCountClr : 1; USHORT FifoTest : 1; } TRANSFER_CONTROL, *PTRANSFER_CONTROL; typedef struct _TRANSFER_STATUS { // #2 USHORT Reserved4 : 8; // same as TRASNFER_CONTROL USHORT Reserved5 : 4; USHORT FifoTrueFull : 1; USHORT FifoTrueEmpty : 1; USHORT Reserved6 : 2; } TRANSFER_STATUS, *PTRANSFER_STATUS; typedef struct _TIMER_SET_READ { // #6 USHORT TimerCnt : 8; USHORT TimerStop : 1; USHORT Reserved7 : 7; } TIMER_SET_READ, *PTIMER_SET_READ; typedef struct SCSI_BUS_CONTROL { // #10 UCHAR ScsiSel : 1; UCHAR ScsiRst : 1; UCHAR ScsiDataOutEnb : 1; UCHAR ScsiATN : 1; UCHAR ScsiACK : 1; UCHAR ScsiBSY : 1; UCHAR AutoDirection : 1; UCHAR AckEnb : 1; } SCSI_BUS_CONTROL, *PSCSI_BUS_CONTROL; typedef struct _CLR_COUNTER { // #12 UCHAR AckCounterClear : 1; UCHAR ReqCounterClear : 1; UCHAR FifoHostPointerClr : 1; UCHAR FifoRestCountClr : 1; UCHAR BmCountClr : 1; UCHAR SavedAckCountClr : 1; UCHAR Reserved8 : 2; } CLR_COUNTER, *PCLR_COUNTER; typedef struct _SCSI_BUS_MONITOR { // #12 UCHAR Scsi_MSG : 1; UCHAR Scsi_I_O : 1; UCHAR Scsi_C_D : 1; UCHAR Scsi_BSY : 1; UCHAR Scsi_ACK : 1; UCHAR Scsi_REQ : 1; UCHAR Scsi_SEL : 1; UCHAR Scsi_ATN : 1; } SCSI_BUS_MONITOR, *PSCSI_BUS_MONITOR; typedef struct _PARITY_CONTROL { // #16 UCHAR ParityCheckEnable : 1; UCHAR ParityErrorClear : 1; UCHAR Reserved9 : 6; } PARITY_CONTROL, *PPARITY_CONTROL; typedef struct _PARITY_STATUS { // #16 UCHAR Reserved10 : 1; // same as PARITY_CONTROL #ifdef NINJA32UDE UCHAR ParityError_LSB : 1; // chg UCHAR ParityError_MSB : 1; // new UCHAR Reserved11 : 5; #else // NINJA32UDE UCHAR ParityError : 1; UCHAR Reserved11 : 6; #endif // NINJA32UDE } PARITY_STATUS, *PPARITY_STATUS; typedef struct _COMMAND_CONTROL { // #18 USHORT ClrCdbFifoPointer : 1; USHORT AutoCommandPhase : 1; USHORT AutoScsiStart : 1; USHORT AutoScsiRestart : 1; USHORT AutoParameter : 1; USHORT AutoATN : 1; USHORT AutoMsgin00_04 : 1; USHORT AutoMsgin02 : 1; USHORT AutoMsgin03 : 1; USHORT Reserved12 : 7; } COMMAND_CONTROL, *PCOMMAND_CONTROL; typedef struct _SET_ARBIT { // #1a UCHAR ArbitGo : 1; UCHAR ArbitFlagClear : 1; UCHAR Reserved13 : 6; } SET_ARBIT, *PSET_ARBIT; typedef struct _ARBIT_STATUS { // #1a UCHAR ArbitGoStatus : 1; UCHAR ArbitWin : 1; UCHAR ArbitFail : 1; UCHAR AutoParameterValid : 1; UCHAR SgTableValid : 1; UCHAR Reserved14 : 3; } ARBIT_STATUS, *PARBIT_STATUS; typedef struct _SYNC_REG { // #1c UCHAR SyncOffset : 4; UCHAR SyncPeriod : 4; } SYNC_REG, *PSYNC_REG; typedef struct _ACK_WIDTH { // #1d UCHAR AckPulse : 2; UCHAR Reserved15 : 6; } ACK_WIDTH, *PACK_WIDTH; typedef struct _SCAM_CONTROL { // #24 UCHAR ScamMSG : 1; UCHAR ScamI_O : 1; UCHAR ScamC_D : 1; UCHAR ScamBSY : 1; UCHAR ScamSEL : 1; UCHAR ScamXferOk : 1; UCHAR Reserved16 : 2; } SCAM_CONTROL, *PSCAM_CONTROL; typedef struct _FIFO_REST_CNT { // #0c USHORT FifoRestCnt : 9; USHORT Reserved17 : 5; USHORT FifoEmptyShld : 1; USHORT FifoFullShld : 1; } FIFO_REST_CNT, *PFIFO_REST_CNT; typedef struct _SREQ_SMPL_RATE { // #0F UCHAR SreqRate : 2; UCHAR SamplingEnable : 1; UCHAR Reserved18 : 5; } SREQ_SMPL_RATE, *PSREQ_SMPL_RATE; typedef struct _SCSI_EXECUTE_PHASE { // #40 USHORT CommandPhase : 1; USHORT DataInPhase : 1; USHORT DataOutPhase : 1; USHORT MsgOutPhase : 1; USHORT StatusPhase : 1; USHORT IllegalPhase : 1; USHORT BusFree : 1; USHORT PausedMsgIN : 1; USHORT PausedMsgOut : 1; USHORT SelectionTimeout : 1; USHORT MsgIn00Valid : 1; USHORT MsgIn02Valid : 1; USHORT MsgIn03Valid : 1; USHORT MsgIn04Valid : 1; USHORT Reserved19 : 1; USHORT AutoScsiBusy : 1; } SCSI_EXECUTE_PHASE, *PSCSI_EXECUTE_PHASE; #ifdef NINJA32UDE typedef struct _HTOS_DATA_FACTOR { // #50 new UCHAR DelayFactor : 3; UCHAR Reserved30 : 4; UCHAR DataSelector : 1; } HTOS_DATA_FACTOR, *PHTOS_DATA_FACTOR; #endif // NINJA32UDE typedef struct _CLOCK_DIV { // index 00 UCHAR ClkDivider : 2; UCHAR Reserved20 : 5; UCHAR ScsiXferClkSelect : 1; } CLOCK_DIV, *PCLOCK_DIV; typedef struct _TermPwrControl { // index 01 UCHAR TermPowerOn : 1; UCHAR TermPowerSense : 1; UCHAR Reserved21 : 5; } TermPwrControl, *PTermPwrControl; typedef struct _IRQ_SELECT { // index 04 USHORT ReselectIrqSel : 1; USHORT PhaseChgIrqSel : 1; USHORT ScsiResetIrqSel : 1; USHORT TimerIrqSel : 1; USHORT FifoShldIrqSel : 1; USHORT TargetAbortIrqSel : 1; USHORT MasterAbortIrqSel : 1; USHORT SerrIrqSel : 1; USHORT PerrIrqSel : 1; USHORT BmCntErrIrqSel : 1; USHORT AutoScsiSeqIrqSel : 1; USHORT Reserved22 : 5; } IRQ_SELECT, *PIRQ_SELECT; typedef struct _OLD_SCSI_PHASE { // index 05 UCHAR OldMSG : 1; UCHAR OldI_O : 1; UCHAR OldC_D : 1; UCHAR OldBusy : 1; UCHAR Reserved23 : 4; } OLD_SCSI_PHASE, *POLD_SCSI_PHASE; typedef struct _CHIP_MODE { // index 0b UCHAR MODE : 1; UCHAR OEM0 : 1; UCHAR OEM1 : 1; UCHAR OPTB : 1; UCHAR OPTC : 1; UCHAR OPTD : 1; UCHAR OPTE : 1; UCHAR OPTF : 1; } CHIP_MODE, *PCHIP_MODE; typedef struct _MISC_REG { // index 0c UCHAR ScsiDirDetector : 1; UCHAR Scsi2Host : 1; UCHAR Host2Scsi : 1; UCHAR DelayedBMStart : 1; UCHAR MasterTerm : 1; UCHAR BMReqTiming : 1; UCHAR AutoSelTiming : 1; #ifdef NINJA32UDE USHORT MAbortMask : 1; // new USHORT BmStop_NDataPhase : 1; // new #else // NINJA32UDE UCHAR Reserved24 : 1; #endif // NINJA32UDE } MISC_REG, *PMISC_REG; typedef struct _BM_CYCLE { // index 0d UCHAR BmCycle : 2; UCHAR FrameAssertTiming : 1; UCHAR IrdyAssertTiming : 1; UCHAR SingleBusmaster : 1; UCHAR MemRdCmd0 : 1; UCHAR SGTAutoParaMemRd : 1; UCHAR MemRdCmd1 : 1; } BM_CYCLE, *PBM_CYCLE; typedef struct _SYNC_TABLE { UCHAR StartPeriod; UCHAR EndPeriod; UCHAR TransferPeriod; UCHAR AckWidth; } SYNC_TABLE,*PSYNC_TABLE; #ifndef NT_INST // for PC CARD typedef struct _PWRENTRY { BYTE PowerLevel; BYTE ValidSignals; } PWRENTRY; typedef struct _ACHARTBL { WORD AdpCaps; DWORD ActiveHigh; DWORD ActiveLow; } ACHARTBL; typedef struct _AINQADAPTOR { WORD wBufferLength; WORD wDataLength; ACHARTBL CharTable; WORD wNumPwrEntries; PWRENTRY PwrEntry; } AINQADAPTOR; #endif typedef struct _IOP_SG_TABLE { ULONG BlockCount; ULONG BufferAddress; } IOP_SG_TABLE,*PIOP_SG_TABLE; typedef struct _FIFO_TEST { UCHAR XferMode; UCHAR Rate; } FIFO_TEST,*PFIFO_TEST; typedef struct _FAST_MODE { UCHAR XferMode; UCHAR Rate; UCHAR PcicTiming; UCHAR MemorySpeed; } FAST_MODE,*PFAST_MODE; typedef struct _SG_TABLE { ULONG Address; ULONG Length; } SG_TABLE, *PSG_TABLE; typedef struct _SG_LIST { SG_TABLE TransferDataBuffer[MAX_SG_LIST]; UCHAR Reserved[8]; } SG_LIST, *PSG_LIST; typedef struct _AUTO_PARA_CDB { UCHAR CDB0; UCHAR Reserved0; UCHAR Reserved1; UCHAR Reserved2; } AUTO_PARA_CDB,*PAUTO_PARA_CDB; typedef struct _AUTO_PARA { AUTO_PARA_CDB Cdb[16]; ULONG ScsiMsgOut; USHORT CommandControl; USHORT TransferControl; UCHAR SyncReg; UCHAR AckWidth; UCHAR TargetId; UCHAR SmplRate; ULONG SgAdr; } AUTO_PARA,*PAUTO_PARA; typedef struct _NONCACHED_EXTENSION{ UCHAR Address[0x10000]; ULONG Reserved; } NONCACHED_EXTENSION,*PNONCACHED_EXTENSION; typedef struct _SRB_BUFFER { //xxx SRB_IO_CONTROL sic; UCHAR TermPower; UCHAR XferMode; UCHAR XferWidth; UCHAR ScsiCable; UCHAR PcicTiming0; UCHAR PcicTiming1; UCHAR PcicMmSpeed; } SRB_BUFFER, *PSRB_BUFFER; // // Logical Unit states. // typedef enum _SCSI_STATE { SC_UNDETERMINED, SC_SELECT, SC_COMMAND, SC_DATA, SC_STATUS, SC_MSG_IN, SC_MSG_OUT, SC_COMPLETE, SC_COMPLETE_OK, SC_BUSFREE, SC_DISCONNECT, SC_RESELECT, SC_RESET } SCSI_STATE, *PSCSI_STATE; typedef struct _SPECIFIC_DEVICE_EXTENSION SPECIFIC_DEVICE_EXTENSION; typedef struct _SPECIFIC_DEVICE_EXTENSION *PSPECIFIC_DEVICE_EXTENSION; // // Logical Unit extension // typedef struct _SPECIFIC_LU_EXTENSION { ULONG SavedDataPointer; // Current data pointer. ULONG SavedDataLength; // Current data lenght. Scsi_Cmnd *ActiveLuRequest; // Active Srb for this LUN. ULONG PhaseWaitCounter; ULONG TransferedLength; ULONG AckCounter; void (*pXferRead) (IN PSPECIFIC_DEVICE_EXTENSION DeviceExtension, ULONG Buffer, ULONG xferLength ); void (*pXferWrite) (IN PSPECIFIC_DEVICE_EXTENSION DeviceExtension, ULONG Buffer, ULONG xferLength ); IOP_SG_TABLE IOP_SG_LIST[18]; ULONG SG_Count; UCHAR XferMode; ULONG Current_SG_Entry; ULONG SGListCount; PVOID SrbExtension; /* 0608 SG_LIST sGlist; */ PSG_LIST pSGlist; ULONG PhySrbExtension; ULONG PhySGlist; BOOLEAN NextReq; #ifdef NINJA32UDE UCHAR TargetFlags; //+[ude] #endif } SPECIFIC_LU_EXTENSION, *PSPECIFIC_LU_EXTENSION; typedef struct _SPECIFIC_DEVICE_EXTENSION nin_softc, *pnin_softc; #ifdef USE_PRAGMAPACK #pragma pack() // 0604 #endif // USE_PRAGMAPACK // // specific per target controller information. // typedef struct _SPECIFIC_TARGET_EXTENSION { UCHAR TargetFlags; UCHAR SynchronousPeriod; UCHAR SynchronousOffset; UCHAR AckWidth; UCHAR SreqSmplRate; UCHAR TransferMode; UCHAR FastScsi; // 0:async/fast, 1:fast20 UCHAR WideScsi; // 0:8bit , 1:16bit UCHAR TargetSrbFlags; #ifdef NINJA32UDE UCHAR SyncMax; // +[ude] #endif // NINJA32UDE }SPECIFIC_TARGET_EXTENSION, *PSPECIFIC_TARGET_EXTENSION; #ifdef NINS32DBG IRQ_STATUS IntIrqStatus; #define DevIntIrqStatus IntIrqStatus #else #define DevIntIrqStatus DeviceExtension->IntIrqStatus #endif // // Device extension // typedef struct _SPECIFIC_DEVICE_EXTENSION { PSCSI_REGISTER BaseAddress; // Port address of adapter. SCSI_STATE ScsiState; ULONG CurDataPointer; // Current pointer for active LUN. ULONG CurDataLength; // Bytes left to xfer to this LUN. PSPECIFIC_LU_EXTENSION ActiveLogicalUnit; // Currently active LUN. UCHAR PathId; BOOLEAN InterruptPending; // Waiting for interrupt. BOOLEAN DmaPending; // Waiting for DMA setup. UCHAR DeviceType[8]; // inquiry data save SPECIFIC_TARGET_EXTENSION TargetState[8]; UCHAR TimerCycle; UCHAR TimerCount; UCHAR TransferMode; UCHAR MessageBuffer[8]; UCHAR MsgOutBuffer[8]; ULONG MessageCount; ULONG MsgOutCount; ULONG MessageSent; ULONG SmitBuffer; UCHAR TargetId; UCHAR TargetLun; USHORT IrqMaskData; UCHAR ScsiPrePhase; USHORT AdapterOption; void (*pXferRead) (IN PSPECIFIC_DEVICE_EXTENSION DeviceExtension, ULONG Buffer, ULONG xferLength ); void (*pXferWrite) (IN PSPECIFIC_DEVICE_EXTENSION DeviceExtension, ULONG Buffer, ULONG xferLength ); BOOLEAN IntWait; BOOLEAN ScsiCable; UCHAR SynchronousPeriod; ULONG AdapterFlags; // +[v1.10] vv Scsi_Cmnd *NextSrbRequest; UCHAR bTermSence; UCHAR bPcicSetup; UCHAR bPcicCmd; UCHAR bMmSpeed; ULONG DevNode; PNONCACHED_EXTENSION NonCachedExtension; ULONG NonCachedPhysical; ULONG MCLK; ULONG mmioReg; IRQ_SELECT wIrqSelect; ULONG NumConnect; IRQ_STATUS IntIrqStatus; BOOLEAN ConCheckDone; UCHAR PollingMode; // 0xff:checking, 0:no , 0x7f:polling UCHAR Latency; //+[v1.01] unsigned int irq; /* IRQ for this adapter */ struct pci_dev *pdev; unsigned char pci_bus; unsigned char pci_device_fn; struct Scsi_Host *host; /* pointer to scsi host */ int host_no; /* SCSI host number */ unsigned long mbase; /* I/O memory address */ unsigned long base; /* card base address */ volatile unsigned char *maddr; /* memory mapped address */ struct timer_list dev_timer; struct timer_list dev_timer2; IRQ_STATUS intIrqStatus2; SCSI_EXECUTE_PHASE scsiExec; PVOID SrbExtension; #ifdef NINJA32UDE SPECIFIC_LU_EXTENSION MyLuExtension; UCHAR DevMap; UCHAR DataNzCan; UCHAR SreqNzCan; UCHAR SreqDelay; UCHAR SackDelay; UCHAR HtoSDelay; UCHAR StoHDelay; ULONG ResetTimer; // +[ude] ^^^ #endif // NINJA32UDE } nanana; typedef SPECIFIC_DEVICE_EXTENSION nins32_host; typedef PSPECIFIC_DEVICE_EXTENSION pnins32_host; // SCSI inquiry data typedef struct _INQUIRYDATA { UCHAR DeviceType :5; UCHAR DeviceTypeQualifier :3; UCHAR DeviceTypeModifier :7; UCHAR RemovableMedia :1; UCHAR Versions; UCHAR ResponseDataFormat; UCHAR AdditionalLength; UCHAR Reserved[2]; UCHAR SoftReset :1; UCHAR CommandQueue :1; UCHAR Reserved2 :1; UCHAR LinkedCommands :1; UCHAR Synchronous :1; UCHAR Wide16Bit :1; UCHAR Wide32Bit :1; UCHAR RelativeAddressing :1; UCHAR VendorId[8]; UCHAR ProductId[16]; UCHAR ProductRevisionLevel[4]; UCHAR VendorSpecific[20]; UCHAR Reserved3[40]; } INQUIRYDATA, *PINQUIRYDATA; typedef struct _SCSI_EXMSG { u_char InitialMessageCode; u_char MessageLength; u_char MessageType; union _EXTENDED_ARGUMENTS { struct { u_char Modifier/*modifier*/[4]; } Modify/*MODIFY*/; struct { u_char TransferPeriod; u_char ReqAckOffset; } Synchronous/*SYNCS*/; struct{ u_char Width; } WIDE; } ExtendedArguments;/*ExArg*/ }SCSI_EXMSG, *PSCSI_EXMSG; typedef SCSI_EXMSG SCSI_EXTENDED_MESSAGE; typedef PSCSI_EXMSG PSCSI_EXTENDED_MESSAGE; // -------------------------------------------------------- // -------------------------------------------------------- // macro ------------------------------------------------ // -------------------------------------------------------- // -------------------------------------------------------- #define SCSI_READ(Dev, Register) inb((Dev)->base + (UCHAR)( &(((PSCSI_REGISTER) 0)->Register))) #define SCSI_READW(Dev, Register) inw((Dev)->base+( (UCHAR) &(((PSCSI_REGISTER) 0)->Register))) #define SCSI_READD(Dev, Register) inl((Dev)->base+( (UCHAR) &(((PSCSI_REGISTER) 0)->Register))) #define SCSI_WRITE(Dev, Register, Value) outb((unsigned)Value,(Dev)->base+((UCHAR) &(((PSCSI_REGISTER) 0)->Register))) #define SCSI_WRITEW(Dev, Register, Value) outw((WORD)Value,(Dev)->base+((UCHAR) &(((PSCSI_REGISTER) 0)->Register))) #define SCSI_WRITED(Dev, Register, Value) outl((DWORD)Value,(Dev)->base+((UCHAR) &(((PSCSI_REGISTER) 0)->Register))) #define SCSI_READ_FIFO(DEVEXT,BUFFER,COUNT) insb(( DEVEXT->base+((UCHAR) &(((PSCSI_REGISTER) 0)->_30.b.pbFifoData))), (void *)BUFFER, COUNT) #define SCSI_WRITE_FIFO(DEVEXT,BUFFER,COUNT) outsb(( ((PSCSI_REGISTER)(DEVEXT->maddr))->_30.b.pbFifoData), BUFFER, COUNT) #define SCSI_WRITE_FIFOW(BASE, BUFFER, COUNT) {outsw((((DEVEXT->maddr)->_30.pwFifoData),BUFFER,(COUNT>>1)); } #define SCSI_WRITE_FIFOD(DEVEXT,BUFFER,COUNT) outsl(( DEVEXT->base+((UCHAR) &(((PSCSI_REGISTER) 0)->_30.pwFifoData))), (void *)BUFFER, (COUNT >> 2)) #define SCSI_READ_FIFOD(DEVEXT,BUFFER,COUNT) insl(( DEVEXT->base+((UCHAR) &(((PSCSI_REGISTER) 0)->_30.pwFifoData))), (void *)BUFFER, (COUNT >> 2)) #define SCSI_SREAD(ChipAddr, Register) ( ( ((ChipAddr)->pIndexReg)=(UCHAR) &(((PSUBREGS) 0)->Register) ),((ChipAddr)->pDataRegL)) #define SCSI_SWRITE(ChipAddr, Register, Value) { ( ( (ChipAddr)->pIndexReg )=(UCHAR) &(((PSUBREGS) 0)->Register) ); ( ((ChipAddr)->pDataRegL)=Value );} #define SCSI_SREADW(ChipAddr, Register) ( ( ((ChipAddr)->pIndexReg)=(UCHAR) &(((PSUBREGS) 0)->Register) ),((ChipAddr)->pDataRegL)) #define SCSI_SWRITEW(ChipAddr, Register, Value) { ( ((ChipAddr)->pIndexReg)=(UCHAR) &(((PSUBREGS) 0)->Register) ); ( ((ChipAddr)->pDataRegL)=(Value) );} #define SCSI_SREADD(ChipAddr, Register) ( ( ((ChipAddr)->pIndexReg)=(UCHAR) &( ((PSUBREGS) 0)->Register) ),/*((PUSHORT)((ChipAddr)->pDataRegL) |*/ ( ((PUSHORT)((ChipAddr)->pDataRegH)) << 16) ) #define SCSI_SWRITED(ChipAddr, Register) ( ( ((ChipAddr)->pIndexReg)=(UCHAR) &(((PSUBREGS) 0)->Register) ), ( ((ChipAddr)->pDataRegL)=(USHORT)(Value & 0xffff) ),(((ChipAddr)->pDataRegH)=(USHORT)(Value >> 16)) // -------------------------------------------------------- // -------------------------------------------------------- // macro ------------------------------------------------ // -------------------------------------------------------- // -------------------------------------------------------- #if NINS32DBG /* // // Globals and externals used for debugging. // // // Ns3Debug affects which debug prints are enabled: // // 0x001 Arbitration and selection // 0x002 Command, status // 0x004 Data transfer // 0x008 Message in // 0x010 Miniport entry points and completion // 0x020 Initialization and interrupt // 0x040 StatusCheck and WaitForRequest // 0x080 Control register manipulation // 0x100 Completion // 0x200 Phase info // 0x400 Temporary // 0x800 Panic // 0x1000 Ns3Interrupt // 0x2000 Ns3SpotWrite // 0x4000 Ns3SpotRead // */ /* 0608 #define Ns3Debug NINS32DBG #define Ns3DebugPrint(MASK, ARGS) if (MASK & Ns3Debug) { printk ARGS;} */ #define Ns3DebugPrint(MASK, ARGS) if (MASK & NINS32DBG) { printk ARGS;} #else #define Ns3DebugPrint(MASK, ARGS) #endif #define ScsiPortWriteRegisterBufferUchar(SRC,DST,LEN) for(i=0;i